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DVB Standard#

Digital Video Broadcasting (DVB) is a complete digital television solution that includes DVB-C (Digital Television Cable Transmission Standard), DVB-T (Digital Television Terrestrial Transmission Standard), and DVB-S (Digital Television Satellite Transmission Standard). The focus here is on the DVB-S system.

DVB-S is the digital satellite broadcasting standard, which has advantages such as wide coverage and large program capacity. The signal uses RS(188,204) and convolutional coding in a concatenated manner, with QPSK modulation.

Basic Principles of DVB-S Channel Coding and Modulation#

Principle Block Diagram#

According to the ETSI DVB-S standard, the principle block diagram is shown below.

Due to the significant impact of power limitations on DTH services provided by satellites, the main design goal should be noise and interference resistance rather than spectral efficiency. To achieve high energy efficiency without excessively compromising spectral efficiency, the system should use QPSK modulation along with convolutional codes and RS codes in a concatenated manner.

Interface#

Channel Coding#

TS Stream Adaptation Unit (Adaptation)#

The input TS stream is packaged according to the MPEG-2 format with a fixed length, where the packet length is 188, and the frame header is a sync word $47_{hex}$. The DVB-S standard requires that every 8 TS packets form a superframe, reversing the 8 sync headers in the superframe to $b8_{hex}$, while the remaining sync headers remain unchanged. Additionally, empty packets are automatically inserted, adding 16 zeros after the data packet to extend the length of the 188-length data packet to a length of 204, establishing clock matching and interface connection with the subsequent channel coding module.

Scrambling Unit (Energy Dispersal)#

The baseband signal contains many sequences of consecutive "1s" or "0s," which can lead to a significant amount of low-frequency components in the baseband signal spectrum, making it unfavorable for signal transmission in the channel and for clock signal extraction at the receiver. Therefore, scrambling is used to convert the TS stream into a pseudo-random sequence. The schematic diagram of randomization in the DVB-S standard is as follows:

The polynomial for generating the pseudo-random binary sequence is as follows:

The scrambling is processed in units of superframes composed of 8 data packets. At the start of processing each unit, the sequence $"100101010000000"$ is loaded into the register for scrambling. The sync word of the data packet is not scrambled.

RS Coding#

The outer code uses RS coding, which has the ability to correct both random and burst errors, with a more effective correction for burst errors. The coding format used in DVB-S is RS(239,255) truncated to obtain RS(188,204) coding, with a maximum correctable length of 8 bytes, and the coding starts from the sync word $47_{hex}$ or $b8_{hex}$.

Brief Description of the Coding Principle#

Assuming the information polynomial is

The code generation polynomial is

where $a = 02_{hex}$, thus the expanded form of the generating polynomial is

After dividing $x^{16}\cdot m(x)$ by $g(x)$, the remainder is a polynomial of degree 15 in $x$, and its 16 coefficients are the generated 16 check bytes, which are added to the 188-length data packet to complete the $RS(188,204)$ coding.

Convolutional Interleaving#

During the digital signal transmission process, some burst interference can lead to a series of data errors that may exceed the error correction range of the RS code. Convolutional interleaving can spread out erroneous characters, making the channel behave like an approximately memoryless channel. The convolutional interleaving used in DVB-S has an interleaving depth of 12. The block diagram of interleaving and deinterleaving is as follows:

Convolutional Coding#

The inner code uses a $(2,1,7)$ type convolutional code, with a coding efficiency of $\frac{k}{n}=\frac{1}{2}$, consisting of 6 shift registers and 2 modulo-2 adders, where 1 bit signal generates 2 bits of coded signal, with a constraint length of 7.

When the channel quality is good, the coded signal can be punctured to improve channel utilization.

Matlab Simulation#

TS Stream Adaptation and Scrambling Module#

CLKdivide#

The bitrate of a high-definition television signal is $8Mbps$, so the rate of the binary signal is $8Mbps$. The input data is of type $uint8$, so the input signal rate is $1M$. Therefore, the CLKdivide module divides the $200MHz$ clock down to $1MHz$ and $8MHz$.

sigSource#

This module generates the input TS stream signal and produces the start, end, and enable signals for RS coding. Since an empty packet needs to be inserted after each output of a 188-byte length data packet, an enable system is used, which pulls down the enable signal to insert an empty packet after counting 188 times.

HeaderProcess#

This module performs rate conversion on the input TS stream and groups superframes, combining every eight data packets into one superframe and reversing the first sync word from $0x47$ to $0xb8$, while generating the enable signal for sigSource. It also generates control signals for the scrambling module.

The first Multiport Switch is used to insert empty packets, while the second Multiport Switch is used to reverse the first sync word of the superframe.

myScrambler#

Designed according to the generating polynomial of the scrambling. The enable signal generated by HeaderProcess is pulled low exactly when the input sync word is received, and no scrambling is performed. The scrambling reset signal reloads the initial sequence "100101010000000" after one superframe has been input.

Simulation Data#

RS Coding Module#

Using the module from HDL Coder, since the clock rate is $200 MHz$, a triggering module needs to be added to ensure that RS coding is performed at the symbol rate $R_B$.

Convolutional Interleaving#

Similarly, a triggering module is added to ensure that the interleaving speed is at the symbol rate $R_B$.

uint8 to binary Module#

First, the input data is bitwise ANDed to extract each bit of data, which is then output bit by bit using a Multiport Switch. The enable rate of the counter is 8 times the symbol rate $R_B$.

Convolutional Coding#

If no puncturing is performed, the coding efficiency is $\frac{1}{2}$. Puncturing can also be performed to achieve coding efficiencies of $\frac{2}{3}, \frac{3}{4}, \frac{5}{6}, \frac{7}{8}$. Within a certain bandwidth, the greater the coding efficiency, the greater the transmission efficiency, while the error correction capability decreases.

Vivado Implementation#

Most of the Vivado code is generated by HDL Coder or generated coefficient files from Matlab, which are then imported into Vivado's IP cores.

DataSource_Scrambler#

When generating HDL code directly, the sigSource module in the DataSource_Scrambler module does not meet timing requirements due to the setup time at a frequency of $200 MHz$. Therefore, the following configuration is made before generating HDL:

After adding a pipeline stage at the output, the timing can pass after synthesis and routing. Additionally, a delay module is added at all output signal points of this module to form a pipeline.

Scrambling Module#

It can be seen that after every 8 data packets are input, the initial value of the D flip-flops inside the scrambler is reset, while the reversed sync word $0xb8$ is not scrambled.

Data Alignment#

During the simulation process, it was found that the sync word $0xb8$ and the enable signal for RS coding were not aligned, so the following module was added:

By delaying the output enable signal by one data cycle, the synchronization of the signals can be ensured.

RS Coding#

The data from ModelSim is imported into Matlab for decoding, and it can be seen that the 188 data packets have been completely decoded.

Raised Cosine Roll-off Filter#

Matlab Filter Design#

According to the requirements of the DVB-S standard, the raised cosine roll-off factor is $0.35$, and the filter coefficients are designed using Matlab's filterDesigner tool.

In FPGA, the filter coefficients need to be processed in fixed-point format.

After quantizing the coefficients to 32 bits, the magnitude response is as follows:

After quantizing the coefficients to 16 bits, the magnitude response is as follows:

It can be seen that the magnitude response of the 16-bit quantization is almost the same as that of the 32-bit quantization. To save space, 16-bit quantization is used.

After quantization, click on Target → Xilinx Coefficient File to generate the .coe file.

Vivado FIR Filter Design#

Select Source as COE File.

The input sampling frequency must equal the clock frequency, without oversampling.

In Implementation, select the coefficient type as signed, and set the bit width to $16$.

The input signal is +/-1, so the input bit width is 2, with the first bit as the sign bit. The output mode is set to full precision.

Waveform#

Using XDMA for Data Input and Output Acquisition#

The structural block diagram is shown above.

The overall structure of the project is shown above, with data written into the system through the XDMA M_AXIS_H2C interface. Since the width of the written data is $128bit$, and the input width of the signal processing part in the project is 8bit, an AXISDataWidthConverter module is added to convert the width from 16BYTE to 1BYTE and write it into FIFO. The AXIGPIO module reads the FIFO's almost full signal. If the FIFO is full, the almost full signal is pulled high, stopping data writing. When reading the QPSK signal generated by DVB-S, the signal width has already increased due to raised cosine roll-off filtering and modulation. To reduce complexity, the modulated signal is padded with zeros to 128bit before being output to the Host through the M_AXIS_C2H interface.

The debugging process can be seen at

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