💡 Since my girlfriend is preparing to use FPGA for her undergraduate thesis, I am writing this article to help her quickly get started with HDL coder and reduce the difficulty of initial entry.
Simulink Library Supporting HDL Code Generation#
Modules in libraries that contain HDL in their names can generally be used to generate HDL code. You can directly search for the module name, for example, searching for fir,
You can see which library it is located in next to it. A module may be located in multiple libraries; as long as one of the library names contains HDL, it indicates that this module can be used to generate HDL code.
Some Common Operations#
Create Subsystem#
After dragging the modules from the library to the main interface and arranging them, it may occupy a large space. If the project is large and the modules are increasingly connected, it becomes particularly cumbersome. Therefore, after completing a certain function, you can select all the relevant modules. At this point, three dots will appear in the lower right corner. Hovering the mouse over it will expand and show many different functions. The following image shows an AM modulation process. After selecting all related modules, clicking on "Create Subsystem" will yield the subsystem on the right. The newly generated subsystem is named subsystem, and you can rename it to a clearer and more understandable name.
Observe Signal Waveform of Nodes#
When a certain connection line is selected, three dots will also appear. Hovering the mouse over it will expand, and selecting the WiFi-shaped option will allow you to record the signal on that connection. After running the simulation, clicking the WiFi icon again will open the logic analyzer, allowing you to view the signal on that connection.
After selecting a certain signal in the logic analyzer, you can adjust settings such as number system and height in the waveform.
You can also use the scope template to view node signals.
Spectrum Analysis#
Use the Spectrum Analyzer module for spectrum analysis.
When the number of samples is relatively small, you can change the estimation method to Welch.
Signal Data Format Display#
It can display the data types and decimal places of the input and output signals of the module.
After selecting the time legend in the sampling time section, different colors will display modules with different sampling rates, which is very useful in multi-rate system design.
Generating HDL Code#
Preliminary Preparation#
Set Diagnostic Type#
In the model settings, select Diagnostics/Sampling Time.
Single-task and multi-task data transfer must be set to error.
Compatibility Check#
Select the target folder for code generation and run the compatibility checker. If there are no issues with the project, the following interface will appear.
Target Platform Selection#
Select the synthesis tool and FPGA series based on the FPGA being used.
Module Settings#
Right-click on the subsystem for which you want to generate code and select HDL Module Properties:
You can set parameters for pipelining, multipliers, etc.
If the generated code cannot meet timing constraints after being compiled in the EDA tool, you can add pipelining to the inputs and outputs.
💡 If the output of the module has feedback signals to previous modules, pipelining cannot be added. For details, see
bookmark
[bookmark](https://blog.sawenmoerjie.top/article/ec96aebc-b5a5-4059-bbef-02f0003e7a45)
Code Generation#
After clicking to generate HDL code for the subsystem, it will automatically compile once, and the command line window will display the following information.
A report will also be generated.
If there are no errors, you can find the generated Verilog code files in the selected folder above.
Import these files into the EDA tool for direct instantiation.
💡 All files must be imported; you cannot just import a module with a specific name!
💡 Be sure to check the report after compiling in the EDA software, especially for large designs, as it is easy to not meet timing requirements. In this case, you need to go back to Simulink to optimize the design. If the timing report indicates that a certain part of Module A does not meet the requirements, then you need to add pipelining in Module A in Simulink. (Note: I have not encountered timing errors in Quartus, possibly because I have not developed large projects in Quartus.)