Architecture of FIR Filter

Dec 29, 2024#FPGA71

AI Translation

This post is translated from Chinese into English through AI.View Original

AI-generated summary

The document discusses various architectures for digital filters optimized for FPGA implementation. 1. **Fully Parallel Systolic Architecture**: This architecture optimizes filters with symmetric, anti-symmetric, and zero coefficients. When symmetric coefficients are equal, they share a DSP block, allowing the use of pre-adders in Xilinx and Altera DSP blocks. 2. **Fully Parallel Transposed Architecture**: This design shares multipliers for coefficients that are equal and eliminates multipliers for zero coefficients, resulting in a fixed filter delay of 6 clock cycles. 3. **Partly Serial Systolic Architecture**: For cases where the delay length (N) is less than the filter order (L), this architecture requires multiple pulsing units and has a delay of M + ceil(L/M) + 5. 4. **Fully Serial Systolic Architecture**: When the delay length is greater than or equal to the filter order, this architecture operates in a fully serial manner with a delay of L + 5. The document includes diagrams illustrating the structures before and after optimization for each architecture.

Fully Parallel Systolic Architecture#

The fully parallel systolic filter optimizes symmetric coefficients, antisymmetric coefficients, and zero coefficients. The filter's delay is influenced by the symmetry of the filter coefficients. When the symmetric coefficients are absolutely equal, they share the same DSP block. This pairing allows the use of pre-adders in the DSP blocks of Xilinx and Altera during implementation. The structure of a symmetric filter, if not suitable for the symmetric coefficient optimization architecture, is shown in the upper part of the figure below, with the optimized version in the lower part:
fir_arch_systolic_sym.png|500

Fully Parallel Transposed Architecture#

The Fully Parallel Transposed Architecture shares multipliers for any coefficients that are absolutely equal while removing the multipliers required for zero coefficients. The filter delay for this structure is a fixed 6 clk. The upper part of the figure below shows the non-optimized symmetric filter, while the lower part shows the optimized structure:
fir_arch_transposed_sym.png|500

Partly Serial Systolic Architecture (1 < N < L)#

Where N is the delay length and L is the filter order. The partly serial filter requires M=ceil(L/N) pulse units, structured as follows:
fir_arch_systolic_partly_serial.png|500
The filter delay is M+ceil(L/M)+5. If the coefficients in the lookup table corresponding to a multiplier are 0 or a power of 2, the implementation process does not include the multiplier, and the change in power is achieved through shifting.

Fully Serial Systolic Architecture (N ≥ L)#

If the delay length is greater than the filter order, the filter is in a fully serial structure. The filter delay is $L+5$.
fir_arch_systolic_fully_serial.png|500