Testbench Simulation Script Writing Guide

Note

Since Quartus's VWF simulation can only simulate for a very short time, and Vivado simulation also requires adding stimulus signals, it is necessary to write a testbench file for stimulus simulation.

Testbench File Structure#

The purpose of writing a testbench is to test whether the functionality and performance of the module meet the design expectations. The steps to verify the functionality of the design include:

Generate appropriate stimulus waveforms: The stimulus should typically cover all possible input states that the HDL module under test can produce;
Add the generated stimulus signals to the DUT and observe its response: Instantiate the DUT module in the Testbench and run the simulation test;
Compare the output response with the expected values.
The general structure of a testbench module is as follows:

``` Verilog
module Test_bench_name();
// 01: Signal or variable declaration
// -- Inputs in the logic design correspond to reg type
// -- Outputs in the logic design correspond to wire type
// 02: Use initial or always statements to generate stimulus
// 03: Instantiate the DUT module to be tested
// 04: Monitor and compare output responses
endmodule

Code Example#

Clock Stimulus Input Example#

/*----------------------------------------------------------------
Method 1 for generating clock stimulus: 50% duty cycle clock
----------------------------------------------------------------*/
parameter ClockPeriod=10; // Parameterized clock period
initial
  begin
    clk_i=0;
    forever#(ClockPeriod/2) clk_i = ~clk_i;
end


/*----------------------------------------------------------------
Method 2 for generating clock stimulus: 50% duty cycle clock
----------------------------------------------------------------*/
initial
begin
  clk_i=0;
end
always #(ClockPeriod/2) clk_i=~clk_i;


/*----------------------------------------------------------------
Method 3 for generating clock stimulus: Generate a fixed number of clock pulses
----------------------------------------------------------------*/
parameter ClockPeriod=10; // Parameterized clock period
initial
begin
  clk_i=0;
  repeat(6)
  #(ClockPeriod/2) clk_i=~clk_i;
end


/*----------------------------------------------------------------
Method 4 for generating clock stimulus: Generate a clock with a duty cycle not equal to 50%
----------------------------------------------------------------*/
parameter ClockPeriod=10; // Parameterized clock period
initial
begin
clk_i=0;
forever
  begin
    #((ClockPeriod/2)-2) clk_i=0;
    #((ClockPeriod/2)+2) clk_i=1;
    end
end

Reset Stimulus Input Example#

/*---------------------------------------------------------------- 
Method 1 for generating reset signal: Asynchronous reset
----------------------------------------------------------------*/
initial
begin
  [rs](https://www.elecfans.com/tags/rs/)t_n_i=1;
  #100; rst_n_i=0;
  #100; rst_n_i=1; 
end
/*---------------------------------------------------------------- 
Method 2 for generating reset signal: Synchronous reset
----------------------------------------------------------------*/
initial
begin
  rst_n_i=1; clk_i = 0;
  @(negedge clk_i)
  rst_n_i=0;
  #100; // Fixed time reset
  repeat(10) @(negedge clk_i); // Fixed number of cycles reset
  @(negedge clk_i)
  rst_n_i=1; 
end
always #5 clk_i=~clk_i;


/*---------------------------------------------------------------- 
Method 3 for generating reset signal: Reset task encapsulation
----------------------------------------------------------------*/
task reset;
input [31:0] reset_time; // Adjustable reset time, input reset time
  RST_ING=0; // Adjustable reset method, low level or high level
  begin
    rst_n=RST_ING; // During reset
    #reset_time; // Reset time
    rst_n_i=~RST_ING; // Release reset, reset ends
  end
endtask

Simulation Control Statements and System Task Descriptions#

``` Verilog
/*---------------------------------------------------------------- 
Simulation control statements and system task descriptions
----------------------------------------------------------------*/
$stop  // Stop running the simulation, can continue simulation in modelsim
$stop(n) // Parameterized system task, outputs simulation information based on parameters 0, 1, or 2
$finish // End running the simulation, cannot continue simulation
$finish(n) // Parameterized system task, outputs simulation information based on parameters 0, 1, or 2
//0: No output of any information
//1: Output current simulation time and location
//2: Output current simulation time, location, and statistics of memory and CPU time used during the simulation
$random // Generate random numbers
$random % n // Generate random numbers in the range of -n to n
{$random} % n // Generate random numbers in the range of 0 to n
/*----------------------------------------------------------------

Text Reading#

/*---------------------------------------------------------------- 
Text input methods: $readmemb/$readmemh
----------------------------------------------------------------*/
$readmemb/$readmemh("<data file name>",<memory name>);
$readmemb/$readmemh("<data file name>",<memory name>,<starting address>);
$readmemb/$readmemh("<data file name>",<memory name>,<starting address>,<ending address>);
$readmemb:/* Read binary data, the file content can only contain: whitespace, comment lines, binary numbers
Data cannot contain width specifications and format specifications, each number must be a binary digit. */
$readmemh:/* Read hexadecimal data, the file content can only contain: whitespace, comment lines, hexadecimal numbers
Data cannot contain width specifications and format specifications, each number must be a hexadecimal digit. */