Generating txt files in Matlab for import into Vivado simulation

Jul 14, 2025#MATLAB #FPGA144

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The document describes a process for generating a text file in MATLAB that can be imported into a Vivado simulation for FPGA development. It outlines the steps to convert input data into 8-bit binary format and write it to a text file using the `fopen` function. Various file access permissions for `fopen` are explained, including options for reading, writing, and appending data. Additionally, it provides a sample testbench code for Vivado, including the setup for clock and reset signals, and how to read the generated text file into a memory array. It emphasizes the importance of using forward slashes in file paths within the testbench code to ensure proper file access.

Matlab Processes Data and Writes to txt File#

%% Txt Generate
pre_RS_data=dec2bin(simDataIn,8);       % Convert data to 8-bit binary
fid=fopen("F:\FPGA\Xilinx_vivado\project\dvbstestbench\dbvs\matlab\pre_RS_data.txt","wt");
for i=1:n*nMessages         % Data length
    fprintf(fid,"%s\n",pre_RS_data(i,1:8));  % Since binary data is 8 bits, it is 1:8
end
fclose(fid);

Use the fopen function to get the file id, the syntax of fopen is as follows

Where permission is the file access type, with the following permissions

`'r'`	Open a file for reading.
`'w'`	Open or create a new file for writing. Discard existing content (if any).
`'a'`	Open or create a new file for writing. Append data to the end of the file.
`'r+'`	Open a file for reading and writing.
`'w+'`	Open or create a new file for reading and writing. Discard existing content (if any).
`'a+'`	Open or create a new file for reading and writing. Append data to the end of the file.
`'A'`	Open a file to append (but do not automatically flush) the current output buffer.
`'W'`	Open a file for writing (but do not automatically flush) the current output buffer.

💡 To open in text mode, append 't'

Testbench Writing in Vivado#

`timescale 1ns/1ps

module top_tb();

reg clk;
reg rst_n;
reg [7:0]SEQ_IN_0;
reg [7:0] data_mem[1:1020];
reg [31:0] i;
wire BIN_OUT;
wire ce_out;
wire locked;

//clk & rst_n gen
initial begin
    clk=1'b0;
    rst_n=1'b0;
    #100
    rst_n=1'b1;  
end
always #5 clk=~clk;

//data read
initial begin
    $readmemb("F:/FPGA/Xilinx_vivado/project/dvbstestbench/dbvs/matlab/pre_RS_data.txt",data_mem);
  
end

initial begin
    i=1;
    forever @(posedge clk) begin
        if(i<1020)  begin
            i=i+1;
        end
        else 
            i=1;
    end
    $display("%s",data_mem[i]);
end

always @(posedge clk) begin
    SEQ_IN_0<=data_mem[i];
end

top_wrapper top_wrapper_u0(
    .clk_0    (clk),
    .rst_n_0  (rst_n),
    .SEQ_IN_0(SEQ_IN_0),
    .BIN_OUT_0  (BIN_OUT),
    .ce_out_0   (ce_out),
    .locked_0   (locked)
);

endmodule

💡 The file path copied directly within the folder uses , but in the testbench, all backslashes must be changed to /; otherwise, the txt file cannot be read.