Level Standards in FPGA - moerjielovecookie

When an FPGA exchanges information with the outside world, it is essential to have a recognized standard for both sending and receiving information to ensure its correctness. In digital circuits, we commonly use high and low voltages to represent "0" and "1". So, what voltage level is considered "1"? At this point, a standard is needed, which is the voltage level standard.

Common Voltage Level Standards#

Logic Level	$V_{CC}/V$	$V_{OH}/V$	$V_{OL}/V$	$V_{IH}/V$	$V_{IL}/V$
TTL	$5.0$	$\geq{2}.4$	$\leq 0.4$	$\ge 2.0$	$\le 0.8$
LVTTL	$3.3$	$\geq2.4$	$\leq 0.4$	$\ge 2.0$	$\le 0.8$
LVTTL	$2.5$	$\geq 2.0$	$\le 0.2$	$\ge 1.7$	$\le 0.7$
CMOS	$5.0$	$\geq 4.45$	$\leq 0.5$	$\ge 3.5$	$\le 1.5$
LVCMOS	$3.3$	$\ge 3.2$	$\leq 0.1$	$\ge 2.0$	$\le 0.7$
LVCMOS	$2.5$	$\ge 2.0$	$\le 0.1$	$\ge 1.7$	$\le 0.7$
RS 232	$\pm 12 \sim 15$	$-3\sim-15$	$3\sim 15$	$-3\sim-15$	$3\sim 15$

TTL#

TTL (Transistor - Transistor Logic) is a veteran member of the voltage level standards. It was widely used in early digital circuits, but it has some drawbacks, such as a large voltage space between the high-level decision threshold and the supply voltage, which can lead to signal instability; moreover, the 5 V voltage consumes too much power.

LVTTL#

LVTTL (Low Voltage Transistor - Transistor Logic) improves upon the drawbacks of TTL by changing the supply voltage to $3.3V$, which also reduces power consumption and enhances signal stability.

CMOS#

CMOS (Complementary Metal Oxide Semiconductor) is characterized by low power consumption and the ability to automatically adjust power consumption based on the circuit's operating state.

LVCMOS#

LVCMOS (Low Voltage Complementary Metal Oxide Semiconductor) further reduces the supply voltage and power consumption based on CMOS. LVCMOS is very popular in low-power, medium-low-speed digital circuits.

LVDS#

LVDS, which stands for Low Voltage Differential Signaling, is a voltage level standard that uses low-voltage differential signaling to transmit high-speed signals, characterized by low voltage, low power consumption, and strong noise suppression capabilities. The output voltage swing of LVDS is very small, only $\pm 350mV$, with a current of about $3.5mA$. Due to its ultra-low power consumption and ultra-fast data transmission rates, it is commonly used for high-speed data transmission.